1. Field of the Invention
The invention relates to integrated circuits and more particularly to integrated circuits which employ field effect transistors. More specifically, the invention relates to improved field effect transistor structures and to a process for fabricating same. Still more specifically, the invention relates to an improved monolithic memory and process for fabricating same.
2. Description of the Prior Art
Metal Oxide Semiconductor Field Effect transistors (MOSFETS) or Insulated Gate Field Effect Transistors (IGFETS) are well known in the art. Reference is made to article "Metal-Oxide-Semiconductor Technology" by William C. Hittinger, published in the August 1973 issue of Scientific American, pages 48 through 57. There are numerous patents, published articles and texts which disclose the theory, methods of fabricating and circuit devices utilizing MOSFETS or IGFETS. One such text is "MOSFET in Circuit Design" by Robert H. Crawford (Texas Instruments Electronic Series) McGraw Hill, copyrighted 1967 by Texas Instruments Incorporated. Another text is "Electronics: BJTs, FETs, and Microcircuits" by E. James Angelo, Jr., McGraw-Hill Electrical and Electronic Engineering Series, copyrighted by McGraw-Hill 1969.
The MOSFET or IGFET transistor generally comprises a first semiconductor region in which source and drain regions of opposite conductivity type to the region are disposed. A channel region is defined between the source and drain regions. The channel conductivity is variable in accordance with potentials applied to a gate electrode capacitively coupled thereto through an insulating layer disposed on the channel surface. Field effect type transistors are of increasing interest and commercial importance, particularly because of their high input impedance compared with bipolar transistors and also because a large number of such elements may be economically disposed in a single body of material.
Semiconductor memory arrays have and are receiving considerable attention in the art. Semiconductor memories have numerous advantages over prior art storage devices, such as magnetic cores, in that they require less power to operate and additionally, a greater amount of information may be stored for a given structural volume of physical memory. Among the prior art semiconductor arrays are included those where information is stored on a capacitor, typically parasitic capacitance, and wherein the information must be refreshed periodically. Also among the prior art semiconductor arrays are the type employing a MOS device having a floating gate as a memory element and the type employing a floating avalanche-injection MOS device. Other prior art semiconductor memory devices use flip-flops or circuits equivalent thereto for storing information.
U.S. Pat. No. 3,387,286 granted June 4, 1968 to Robert H. Dennard is directed to a "Field-Effect Transistor Memory". The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are connected to the cells. Each cell is formed, in one embodiment, using a single field-effect transistor and a single capacitor. The gate electrode of the transistor is connected to the word line, the source terminal to the bit line, and the drain terminal directly to one of the electrodes of the capacitor. The other electrode of the capacitor is connected to a reference potential. Information is stored by charging the capacitor through the transistor and information is read out by discharging the capacitor through the transistor. During a write operation the word line, which is connected to the gate of the transistor, is energized to render the transistor conductive between source and drain. If a "zero" is to be stored, the bit line is not energized and the capacitor is not charged. If a "one" is to be stored, the bit line is energized and the capacitor is charged to essentially the potential of the bit line signal. During read operations only the word line is energized and a signal is transmitted to the bit line if a one has been stored previously and the capacitor is charged. Since the charge on the capacitor does leak off, it is necessary to periodically regenerate the information stored in the memory.
In another disclosed embodiment in U.S. Pat. No. 3,387,286, rather than storing a charge in a conventional capacitor, a second field effect transistor is used and the charge is stored in the capacitance between the gate and substrate of this transistor. In this memory, the readout is nondestructive with the charge stored at the gate of the second transistor being used to render that transistor conductive when a binary one is stored, so that the word line signal is transmitted through this second transistor to the bit sense line.
Reference is made to the publication "Integrated High-Speed Read-Only Memory with Slow Electronic Write" by A. S. Faber, IBM Technical Disclosure Bulletin, Vol. 8, No. 3, August 1965, pages 461 and 462.
Reference is made to the publication "Nondestructive Readout Memory Cell Using MOS Transistor" by P. Pleshko, IBM Technical Disclosure Bulletin, Vol. 9, No. 8, January 1966, pages 1142 and 1143.
Reference is made to the publication "Integrated MOS Transistor Random Access Memory" by J. D. Schmidt, Solid State Design, January 1965, pages 21-25.
Reference is made to U.S. Pat. No. 3,461,312 granted Aug. 12, 1969 entitled "Signal Storage Circuit Utilizing Charge Storage Characteristics of Field Effect Transistor", Ser. No. 403,482 filed Oct. 13, 1964 by Arnold Faber et al., and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,593,037 granted July 13, 1971 to Marcial E. Hoff, Jr., directed to "Cell for MOS Random Access Integrated Circuit Memory". The cell is a dynamic storage device which utilizes the parasitic capacitance associated with the lead and gate of an MOS device for storage. The cell is adaptable for use in a memory which has a separate select-write line, select-read line, write data line and read data line.
Reference is made to U.S. Pat. No. 3,720,922 granted Mar. 13, 1973 to Walter F. Kosonocky and entitled "Charge Coupled Memory". The charge coupled memory semiconductor substrate has a plurality of polysilicon storage electrodes, each extending in the column direction and each coupled to the substrate at spaced regions along its length. A plurality of digit lines extending also in the column direction, each digit line capable of acting as a source of minority charge carrier for a column of storage locations. A plurality of word lines extending in the row direction each such line being coupled to a row of storage electrodes. Each such line controlling the flow of minority charge carriers between the respective digit lines and their storage locations along that word line.
Reference is made to U.S. Pat. No. 3,740,732 granted June 19, 1973 to Pierre M. Frandon and directed to a "Dynamic Data Storage Cell". The dynamic data storage cell disclosed in U.S. Pat. No. 3,740,732 requires only one insulated field effect transistor to store binary data. The drain of the FET is connected to a data input line and data is stored at the source node of the transistor by inherent capacitance between the source diffusion and the substrate. The capacitance of the source electrode is enhanced by forming a heavily doped layer to underlie a portion of the source diffusion. Using the substrate as circuit ground enables the fabrication of an array of transistors for a random access memory.
Reference is made to U.S. Pat. No. 3,699,646, entitled "Integrated Circuit Structure and Method for Making Integrated Circuit Structure", granted Oct. 24, 1972 to Leslie L. Vadasz. A method for simultaneously completing the formation of a contact, an interconnect, a gate and a source or drain is disclosed. An integrated circuit field effect structure wherein a diffused silicon area is connected directly to a polysilicon member by conductive silicon and more specifically, the source or drain of one device is directly and continuously connected to the gate of an adjacent device by a conductive silicon member.
Reference is made to U.S. Pat. No. 3,774,176 granted Nov. 20, 1973 to Karl-Ulrich Stein et al. and entitled "Semiconductor Memory Having Single Transistor Storage Elements and a Flip Flop Circuit for the Evaluation and Regeneration of Information". More specifically, U.S. Pat. No. 3,774,176 discloses a dynamic semiconductor memory having a plurality of single transistor storage elements connected to a digit line and respective selection lines, an evaluation and regeneration circuit including a flip-flop having a pair of input/output points, each of the points connected to one of the digit lines, and means connecting the points including a controllable semiconductor switch operable to place the points at equal potentials prior to reading from a selected storage element.
Reference is made to U.S. Pat. No. 3,811,076 granted May 14, 1974 to William M. Smith, Jr. and entitled "Field Effect Transistor Integrated Circuit and Memory." An integrated circuit structure of a field effect transistor serially connected to a capacitor has the capacitor formed by one of the current flow electrodes of the FET and by a polycrystalline silicon (polysilicon) field shield. The structure includes, in a semiconductor (e.g. silicon) substrate, of e.g., P-type conductivity, two spaced apart regions of opposite conductivity type to that of the substrate, e.g., N-type. One of the spaced regions serves as a first plate of the capacitor and as a first current flow electrode of the FET. The other region serves as a second current flow electrode of the FET. A first insulating layer (composite of silicon nitride and silicon dioxide) on the substrate has a polysilicon layer on it covering the two spaced regions and is directly and ohmically electrically connected to the substrate. The portion of the polysilicon layer over the spaced region serving as the first plate of the capacitor serves as the second plate of the capacitor. A second insulating layer covers the polysilicon layer and a second layer of conducting material, e.g., aluminum, is provided on the second insulating layer. The second conductive layer overlies the space between the two spaced regions and serves as a gate electrode for the FET. When employed as a memory circuit, the spaced region of the opposite conductivity type to the substrate which does not serve as the first plate of the capacitor is desirably a diffused bit/sense line and the second conducting layer serves as a word line.
Reference is made to U.S. Pat. No. 3,792,319 granted Feb. 12, 1974 to Frederick Tsang and entitled "PolyCrystalline Silicon Fusible Links for Programmable Read Only Memories". Disclosed is a programmable read-only memory using doped polycrystalline silicon fusible links deposited on the top surface of an insulating (e.g. silicon oxide) layer over an integrated circuit and connected through windows in the insulating layer and/or by a metallization layer. The term "fusible" as here employed refers to electrical energization of the link resulting in said link being rendered electrically discontinuous.
Reference is made to U.S. Pat. No. 3,825,946 granted July 23, 1974 to Dov Frohman--Bentchkowsky and entitled "Electrically Alterable Floating Gate Device and Method for Altering Same". A field effect device having a floating gate which can be charged or discharged electrically is disclosed. A pair of spaced apart regions in a substrate define a channel above which a floating gate is disposed and insulated from the channel. The regions have a conductivity type opposite of the substrate. A second gate is disposed above and insulated from the floating gate. The floating gate may be charged electrically by producing an avalanche breakdown at the junction formed by one of the spaced apart regions and the substrate causing the passage of electrons through the insulation into the floating gate. The floating gate may be discharged by the application of a voltage to the second gate relative to the spaced apart regions and substrate causing the passage of electrons from the floating gate through the insulation onto the second gate.
Reference is made to U.S. Pat. No. 3,943,542 granted Mar. 9, 1976 to Irving T. Ho and Jacob Riseman and entitled "High Reliability, Low Leakage Self-Aligned Silicon Gate FET and Method of Fabricating Same." The gate structure of the FET includes a phosphosilicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.
Reference is made to U.S. Pat. No. 3,983,543 granted Sept. 28, 1976 to William Cordaro and entitled "Random Access Memory Read/Write Buffer Circuits Incorporating Complementary Field Effect Transistors". In U.S. Pat. No. 3,983,543, a Read/Write Circuit for a random access memory integrated circuit chip based on complementary enhancement mode field effect transistor technology is disclosed.
Reference is made to U.S. Pat. No. 3,974,486 granted Aug. 10, 1976 to Huntington W. Curtis and Roger L. Verkuil entitled "Multiplication Mode Bistable Field Effect Transistor and Memory Utilizing Same." Disclosed is a single device memory cell comprising essentially an FET structure. The FET structure has a negative resistance characteristics largely obtained by exploiting an electron hole pair multiplication effect which is enhanced by high substrate doping in conjunction with appropriate biasing of the junctions within the device.
Reference is made to U.S. Pat. No. 3,983,545 granted Sept. 28, 1976 to William Cordaro entitled "Random Access Memory Employing Single Ended Sense Latch for One Device Cell". Disclosed is a random access memory having a plurality of groups of storage cells, each storage cell of each group being adapted to store an electrical manifestation of a binary 1, or an electrical manifestation of a binary 0, a sense latch for each of said groups of storage cells for controllably sensing the binary value 0 or 1 stored in any one of said storage cells included within the group of storage cells with which said sense latch is associated, each of said sense latches comprising: a first field effect transistor directly connected to each cell of a group of storage cells, second, third, fourth and fifth field effect transistors respectively connected to said first field effect transistor and to each of the other ones of said second, third, fourth and fifth field effect transistors, means for controlling the conductivity of said first, second, third, fourth and fifth transistors on a selective basis, whereby a binary 1 or a binary 0 may be read from and restored to any predetermined cell in each group.
Reference is made to U.S. patent application, Ser. No. 617,462, filed Sept. 29, 1975, entitled "Self-Aligned Integrated Circuits" by Anatol Furman, Howard L. Kalter and Johann W. Nagel, issued as U.S. Pat. No. 4,021,789, on May 3, 1977 and of common assignee herewith. The Furman et al application discloses semiconductor integrated circuits, including e.g., field effect transistors and memory cells employing field effect transistors, which are formed by providing at a surface of a semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self-insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide--silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrode of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.
Reference is made to U.S. patent application Ser. No. 671,907, filed Mar. 29, 1976, entitled "Field Effect Transistor Lost Film Fabrication Process" by Arup Bhattacharyya and Ronald Silverman issued as U.S. Pat. No. 4,094,057 on June 13, 1978 and of common assignee herewith. The Bhattacharyya et al patent discloses a process for fabricating transistor memory cell arrays which includes forming a thin oxide which is continuous over the entire area and which is continuously protected from the time it is deposited so that subsequent processing steps will not cause any change in the thickness of the thin oxide except where deliberately desired. The process uses a selected combination of material deposition steps coupled with photoresist masking, anodizing and etching steps. By first depositing a protective masking film and subsequently removing this film in a series of steps, so that this film is lost in the fabrication process, the need for using the dual dielectric insulating layers is eliminated. By eliminating such dual dielectric insulating layers the performance and density of the arrays can be improved. Semiconductor arrays, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of a semiconductor substrate a pair of isolation lines and a plurality of spaced apart conductive lines orthogonal to the isolation lines. The conductive lines are preferably anodically self insulatable. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium, such as silicon dioxide, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrode of the transistors. Other elements may be added to the structure to form, e.g., a memory cell.
The art extensively teaches memory cells comprised of storage Flip-Flop circuits or bistable devices utilizing first and second cross coupled field effect transistors. For example, memory cells of the type employing cross coupled field effect transistors having two stable states of conductivity are disclosed in the following publications: "Integrated High-Speed, Read-Only Memory with Slow Electronic Write" by A. S. Faber, IBM Technical Disclosure Bulletin, Vol. 8, No. 3, August 1965, pages 461 and 462; and "Nondestructive Readout Memory Cell Using MOS Transistors", Vol. 8, No. 8, January 1966, pages 1142 and 1143.
Reference is made to U.S. Pat. No. 3,461,312 entitled "Signal Storage Circuit Utilizing Charge Storage Characteristics of Field Effect Transistors" granted Aug. 12, 1969 to A. S. Farber and C. E. Ruoff and of common assignee herewith. The Farber et al patent discloses a shift register and memory cell utilizing the gate to source capacitance of a field effect transistor for the storage of electrical charge.
As further evidenced by the following patents and publication one device memory cells and monolithic memory arrays employing same are well known to the art:
U.S. Pat. No. 3,514,765 granted May 26, 1976 to A. O. Christensen entitled "Sense Amplifier Comprising Cross Coupled MOSFET's Operating In a Race Mode for Single Device per Bit MOSFET Memories";
U.S. Pat. No. 3,740,732 granted June 19, 1973 to Pierre M. Frandon entitled "Dynamic Data Storage Cell";
U.S. Pat. No. 3,745,539 granted July 10, 1973 to E. E. Davidson, R. D. Lane and J. Saia entitled "Latch Type Regenerative Circuit for Reading A Dynamic Memory Cell";
U.S. Pat. No. 3,774,176 granted Nov. 20, 1973 entitled "Semiconductor Memory Having Single Transistor Storage Elements and a Flip-Flop Circuit for the Evaluation and Regeneration of Information";
U.S. Pat. No. 3,789,371 granted Jan. 19, 1974 to Seymour Markowitz entitled "MOSFET Memory Cell";
U.S. Pat. No. 3,851,317 granted Nov. 26, 1974 to R. A. Kenyon entitled "Double Density Non-Volatile Memory Array";
U.S. Pat. No. 3,983,544 granted Sept. 28, 1976 to R. T. Dennison, L. B. Freeman, H. J. Kelly, P. T. S. Liu entitled "Split Memory Array Sharing Same Sensing and Bit Decode Circuitry";
U.S. Pat. No. 3,992,701 granted Nov. 16, 1976 to S. A. Abbas and R. C. Dockerty entitled "Non-Volatile Memory Cell and Array Using Substrate Current";
U.S. Pat. No. 3,992,704 granted Nov. 16, 1976 to Dieter Kantz entitled "Arrangement for Writing-In Binary Signals into Selected Storage Elements of A MOS-STORE"; and
the published article entitled "Single-Transistor Cell Makes Room for More Memory On A MOS Chip" by Leo Cohen, Robert Green, Kent Smith and J. Leland Seely, Electronics, Aug. 2, 1971, pages 69-75.